Karthikeya Mandava

Hello, I'm

Karthikeya

Design Verification Engineer

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About Me

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Experience

4+ years
Design Verification Engineer

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Education

B.Tech in ECE

Hello! I'm an ECE graduate with a passion for SoC DV. With over 4yrs of experience in the semiconductor industry, I've had the opportunity to work on real-time projects for prominent clients like Intel and Renesas. My expertise lies in test bench development, coverage analysis, low power verification, and debugging techniques. I'm proficient in Verilog HDL, System Verilog, UVM Methodology, and scripting languages like Perl, Python, TCL, and Shell. I'm currently pursuing my Master's degree in Electrical and Computer Engineering, focusing on advanced verification methodologies and hardware-software co-verification. I'm driven by the transformative potential of SoC in advancing technology and aspire to make a meaningful impact in this field.

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Experience

Design Verification

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Computer Architecture

Basic

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SoC Design

Intermediate

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Low Power Design & Verification

Intermediate

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Test Bench Development

Experienced

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Coverage Analysis

Experienced

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Debugging Techniques

Experienced

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Scripting

Experienced

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V, SV, UVM

Experienced

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Protocols

Intermediate

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Knowledge Base

Subjects

Design and Verification

Protocols

Protocols

Verification

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